The invention relates to a method for fabricating a nonvolatile memory device and, more particularly, to a method for fabricating an NAND flash memory device implemented with an advanced self-aligned shallow trench isolation (ASA-STI) method.
There is a great demand for flash memory devices that can electronically program and erase data without periodically refreshing data. In an attempt to develop a large capacity memory device that can store a large amount of data, many researchers are particularly focusing on improving the level of integration of semiconductor memory devices.
NAND flash memory devices are suggested as one approach to achieve a higher level of integration in the semiconductor memory devices. In general, an NAND flash memory device is configured with a string structure where a plurality of memory cells are connected in series and sources/drains are shared between the neighboring memory cells. Different from an NOR flash memory device, the NAND flash memory device sequentially reads information.
The programming and erasing operation of the NAND flash memory device proceeds with injecting or discharging electrons into or from a floating gate while controlling threshold voltages of memory cells according to a Fowler-Nordheim (F-N) tunneling mode. Currently, a method for fabricating a floating gate in a 60 nm-level NAND flash memory device is implemented with the aforementioned ASA-STI method due to the decrease of an overlay margin between an active region and a floating gate.
FIGS. 1A to 1F are cross-sectional views illustrating a conventional ASA-STI method. Referring to FIG. 1A, a tunnel oxide layer 101, a conductive layer 102 (e.g., a polysilicon layer) for use in a floating gate, a buffer oxide layer 103, and a pad nitride layer 104 are sequentially formed on a substrate 100. Referring to FIG. 1B, the pad nitride layer 104, the buffer oxide layer 103, the conductive layer 102, the tunnel oxide layer 101, and the substrate 100 are etched to form trenches 105. Reference numerals 100A, 101A, 102A, 103A, and 104A represent a patterned substrate, a patterned tunnel oxide layer, a patterned conductive layer, a patterned buffer oxide layer, and a patterned pad nitride layer, respectively.
Referring to FIG. 1C, a high density plasma (HDP) liner layer 106 is formed on the above resultant surface profile illustrated in FIG. 1B in a manner to fill a portion of the trenches 105 (see FIG. 1B). A polysilazane (PSZ) layer 107 is formed on the HDP liner layer 106 to completely fill the trenches 105 (see FIG. 1B). Reference letter T1 represents a thickness of the patterned pad nitride layer 104A.
Referring to FIG. 1D, the PSZ layer 107 is chemically and mechanically polished. Reference numerals 107A and 106A represents a planarized PSZ layer and a planarized HDP liner layer, respectively. During the above chemical mechanical polishing (CMP) step, a portion of the patterned pad nitride layer 104A may be removed. Reference numeral 104B and reference letter T2 denote a first remaining pad nitride layer and a thickness of the first remaining pad nitride layer, respectively.
Referring to FIG. 1E, each of the planarized PSZ layer 107A and the planarized HDP liner layer 106A is recessed to a certain depth inside the trenches 105 (see FIG. 1B), so that a remaining PSZ layer 107B remains in a concave shape inside the trenches 105 (see FIG. 1B). Reference numeral 106B represents a remaining HDP liner layer. A HDP layer 108 is formed on the remaining PSZ layer 107B in a manner to completely fill the trenches 105 (see FIG. 1B).
Referring to FIG. 1F, the HDP layer 108 (see FIG. 1E) is planarized by chemical mechanical polishing (CMP). Reference numeral 108A represents a planarized HDP layer. As a result, an isolation structure including the remaining HDP liner layer 106B, the remaining PSZ layer 107B and the planarized HDP layer 108A is provided. During the CMP step, a portion of the first remaining pad nitride layer 104B may be removed. Reference numeral 104C and reference letter T3 denote a second remaining pad nitride layer and a thickness of the second remaining pad nitride layer, respectively.
Although not illustrated, the isolation structure formed in a cell region where memory cells are formed is recessed to adjust an effective field oxide height (EFH). The term ‘EFH’ indicates a distance from the surface of the active region to a dielectric layer.
However, the conventional ASA-STI method may have the following limitations. The ASA-STI method may provide a high aspect ratio compared to a self-aligned shallow trench isolation (SA-STI) method implemented in semiconductor technology for a 70 nm-level or more. Thus, instead of forming the isolation structure with a single HDP layer as in the conventional SA-STI method, the isolation structure is formed in a stack structure including a HDP layer, a PSZ layer, and another HDP layer. In other words, the PSZ layer having a good gap-filling characteristic is formed to secure the gap-fill characteristic in a trench, and the HDP layer that has a higher level of hardness than that of the PSZ layer is formed to fill a remaining portion of the trench. This approach permits simpler control of subsequent processes including CMP and an etching step to adjust the EFH.
However, as illustrated in FIGS. 1D and 1F, in the case of forming the isolation structure in a stack structure including the remaining HDP liner layer 106B, the remaining PSZ layer 107B and the planarized HDP layer 108A, the CMP needs to be performed twice. In detail, the CMP is performed individually after the formation of the PSZ layer 107 and after the formation of the HDP layer 108. When performing the CMP step, the patterned pad nitride layer 104A functioning as a polish stop layer is also removed. However, this removal is not uniform throughout the wafer (i.e., substrate structure). Thus, the EFH may not be controlled uniformly throughout the wafer when etching to adjust the EFH.
FIGS. 2A and 2B illustrate transmission electron microscopic (TEM) images of devices formed through respective ASA-STI and SA-STI methods. In FIG. 2A, a cross-sectional view of the device formed through the ASA-STI method is illustrated. In FIG. 2B, a cross-sectional view of the device formed through the SA-STI method is illustrated. Reference labels “Active,” “Fox,” “F.G.,” “1st P1,” “2nd P1,” and “ONO” represent an active region, a non-active region (i.e., isolation region), a floating gate, first and second polysilicon layers, and a dielectric layer, respectively.
As illustrated in FIG. 2A, the EFH of the device formed through the SA-STI method is higher than the EFH of the device formed through the ASA-STI method. The EFH decrease is not observed uniformly throughout the wafer; rather, the EFH is controlled irregularly depending on the pattern density because of a dishing incidence resulting from a difference in the pattern density. As described above, because the CMP needs to be performed at least twice according to the ASA-STI method, the resultant structure is prone to the dishing incidence. “Dishing” refers to the case where a polish target layer in one region is depressed more than the polish target layer in another region depending on the pattern density difference, so that the polish target layer has a dish shape.
FIG. 3 and FIGS. 4A and 4B illustrate graphs of EFH and threshold voltage distributions per wafer region of a device implemented with the conventional ASA-STI method. In particular, the graph in FIG. 3 shows the EFH distribution within a cell region of the wafer. The X and Y axes represent the number of active regions and the size of the EFH, respectively. The graphs in FIGS. 4A and 4B show the EFH distribution within a cell region of the wafer and the threshold voltage distribution. In FIG. 4A, the X and Y axes represent the number of bit lines and a threshold voltage after a programming operation, respectively, and in FIG. 4B, the X and Y axes represent a threshold voltage and the number of bit lines, respectively.
As illustrated in FIG. 3 and FIGS. 4A and 4B, the EFHs have different sizes for each wafer region. Particularly, a high threshold voltage is observed in an edge region, which is a region where the EFH is adjusted to be the smallest compared to other regions. In detail, as shown in FIG. 4B, when a programming operation is implemented according to an incremental step pulse programming (ISPP) scheme, the cell with low EFH is first completed with the programming operation. Thus, after the programming operation, the threshold voltage of the cell is higher than the other cells.
FIGS. 5A and 5B illustrate TEM images of an EFH within a cell region. In FIG. 5A, a cross-sectional view of an edge portion of the cell region is illustrated. In FIG. 5B, a cross-sectional view of a central portion of the cell region is illustrated. The EFH in the edge portion of the cell region is smaller than the EFH in the central portion thereof.
FIG. 6 illustrates a TEM image of a cell to show limitations associated with a decrease in EFH. The non-uniformity in the EFH within the wafer region may also cause a punch-through event in a dielectric layer interposed between the neighboring floating gates. The dielectric layer is likely to be damaged in the region where the EFH is low. Thus, an electric short circuit event in which a control gate and a substrate are directly connected together may occur. If the electric short circuit occurs, leakage current is likely to occur in this region. The leakage current may impede a stable programming or erasing operation, and this adverse effect may result in device failure, which in turn may decrease device yields.